The displays with advanced functions play an important role in consumer electronic products. Liquid crystal displays serve as the chromatic screens having high resolution, which are widely utilized in mobile phones, personal digital assistants (PDAs), digital still cameras, computer displays, and notebook displays. The shift register, an important electric component in the driving circuit of a liquid crystal display panel, is widely used to drive the display circuits of the liquid crystal display panel. As a result, the design of shift register is closely related to the characteristics of the liquid crystal display panel, such as power consumption and reliability.
FIG. 1 is a conventional electric circuit of a single-stage shift register. The shift register 10 includes a “CK” clock pull-down module 12, a “XCK” clock pull-down module 14, a key clock pull-down module 16, and a self-feedback module 18. The signal phase of the “CK” clock pull-down module 12 is opposite to the signal phase of the “XCK” clock pull-down module 14. The “CK” clock pull-down module 12 is composed of six transistors “T109”, “T110”, “T111”, “T112”, “T113”, and “T122”. While the signal voltage level of the “CK” clock pull-down module 12 is high, i.e. the signal voltage level of the “XCK” clock pull-down module 14 is low, transistors “T112” and “T110” are triggered so that the signal voltage levels of node “P101”, i.e. gate line, and the gate of transistor “T102” are pulled down to voltage level “VSS” via the transistor “T110”. The “XCK” clock pull-down module 14 is composed of six transistors “T103”, “T104”, “T105”, “T106”, “T107”, and “T108”. While the signal voltage level of the “XCK” clock pull-down module 14 is high, i.e. the signal voltage level of the “CK” clock pull-down module 12 is low, transistors “T104” and “T106” are triggered so that the signal voltage levels of node “P101” and the gate of transistor “T102” are pulled down to voltage level “VSS” via the transistor “T106”. The key clock pull-down module 16 is composed of two transistors “T116” and “T117” for pulling down the signal voltage levels of node “P101” and the gate of transistor “T102” to voltage level “VSS” via the transistor “T117” after outputting an output signal to node “P101” at the transistor “T102”. The self-feedback module 18 is composed of five transistors “T115”, “T118”, “T119”, “T120”, and “T121” for outputting a driving signal to the key clock pull-down module 16. The shift register further includes a transistor “T123” for controlling the transmission of the clock signal “CK” to a next driving node “N+1 ST”.
For a conventional shift register, the outputting node “N” is used to output the driving signal to pixels within the panel and the driving node “N+1 ST” is used to output the driving signal to the shift register in the next stage. However, due to the circuit configuration of the conventional shift register, transistors “T102” and “T103” cannot be closed normally when the signal of outputting node “N” cannot be changed due to the short or signal errors happening to the pixels within the panel. Thus, the signal voltage level of the driving node “N+1 ST” synchronously changes in accordance with the voltage level of the clock signal “CK” so that the shift registers in different stages cannot operate normally.
FIGS. 2-4 illustrate timing diagrams of main nodes in conventional single-stage shift register. In FIG. 2, if the waveform “V(N)” in the node “N” and the waveform “V(ST)” in the node “ST” are in normal statuses, the waveform “V(N+1)” in the driving node “N+1 ST” has a normal voltage level and waveform. That is, the waveform “V(N+1)” is a single-triggering square waveform. In FIG. 3, if any short or signal error in the stage “N” occurs to the pixels, the waveform “V(N)” in the node “N” has a fixed high voltage level, the waveform “V(N+1)” in the driving node “N+1 ST” is affected by the waveform “V(N)” in the node “N”. Thus, the waveform “V(N+1)” in the driving node “N+1 ST” has continuous square wave so that the pixels in the stage (N+1) has errors and cannot activate correctly.
In FIG. 4, if the pixels have short circuit or signal error in the stage “N” and thus the waveform “V(N)” in the node “N” has a fixed low voltage level, the waveform “V(N+1)” in the driving node “N+1 ST” is affected by the waveform “V(N)” in the node “N”. Thus, the waveform “V(N+1)” in the driving node “N+1 ST” has a jump and drops off to low voltage level so that the pixels in the stage (N+1) have errors and cannot operate correctly.
Consequently, the driving signal in the next stage (N+1) is affected by the driving signal of the previous stage (N), the driving signal of the next stage (N+1) cannot operate normally while the driving signal of the previous stage (N) has errors. Such situation affects the operation of the driving circuit of the liquid crystal panel and further increase the complexity while performing a test procedure.